Summary
Overview
SRMIC-X1 is a residency-first inference accelerator that treats the active per-token working set as a hardware primitive and prioritizes hot SRAM residency over HBM-bound decode behavior.
Abstract
Technical Abstract
The architecture combines a distributed Hot Residency Memory SRAM tier, a high-bandwidth SRMESH-X interconnect, an HBM cold tier, and an optional CXL warm tier. Hardware residency controllers execute promote, demote, pin, spill, and multicast operations using per-page metadata, while bounded per-region working-set rules keep decode-critical service time stable.
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SEO Keywords
SRMIC-X1 patent, inference chip patent, SRAM residency patent, LLM accelerator patent, decode accelerator architecture patent
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