Summary
Overview
This filing introduces an AgentNIC SmartNIC architecture that moves agent-aware infrastructure control into dedicated hardware. Instead of leaving agent intent parsing, queue steering, retry containment, memory movement, and compliance logging to host software, the device processes agent-level metadata in silicon and autonomously performs bounded dataplane actions under hardware policy control.
Abstract
Technical Abstract
A physical SmartNIC device implements an agent-intent parser, intent descriptor tables, a hardware policy enforcement engine, an agent-aware queue scheduler, a bounded autonomous dataplane engine, a memory-orchestration DMA subsystem, retry-amplification suppression logic, and an audit-chain logging block. The hardware classifies operations using fields such as agent identity, trust class, inference-session state, retry lineage, latency budget, workflow state, memory-transfer intent, and audit requirement, then selectively permits queue assignment, transport selection, memory movement, backoff, quarantine, or escalation while generating verifiable audit records for autonomous actions.
Filing Details
India E-Filing Receipt
The filed receipt records provisional FORM 1 submission for application 202641059276 under filing reference TEMP/E-1/64615/2026-CHE. The e-filing receipt timestamp is 2026-05-09 20:11:41, with receipt docket 69506 and transaction identifier N-0001948236.
Search Context
SEO Keywords
AgentNIC patent, SmartNIC patent, agentic AI hardware patent, AI networking patent, queue steering patent, hardware audit logging patent
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