The Great Light Migration: How AI Is Forcing a Revolution in Data Center Optics
From pluggable transceivers to light woven directly into silicon — the optical interconnect stack is undergoing its most radical transformation in decades. Here is the definitive guide to understanding every step of that journey.
There is a problem hiding in plain sight inside every modern AI data center. It is not about GPU compute, memory bandwidth, or cooling infrastructure. It is about the humble optical transceiver — that small, hot-swappable module you barely notice plugged into the front panel of a switch. For years, these devices have been the unsung heroes of the internet. Now, they are becoming the bottleneck that could determine whether AI scales the way we need it to.
The physics are unforgiving. As data center aggregate switch bandwidth climbs from 12.8 Tb/s to 51.2 Tb/s and beyond, and as AI training clusters interconnect hundreds of thousands of GPUs, the electrical path between the compute die and its optical interface has become a critical liability. Every millimeter of PCB trace attenuates signal, consumes power, and demands sophisticated compensation. The industry's response is a fundamental rethinking of where optics live — not at the edge of the board, but as close to the silicon as physically possible.
This is the story of that rethinking. It unfolds in five distinct acts, each representing a deeper integration of light and silicon: Pluggable → LPO → NPO → CPO → OPO.
Chapter 1: Pluggable Optics — The Incumbent
The pluggable optical transceiver is one of the most successful form factors in networking history. Available in a dizzying alphabet of modules — SFP, QSFP-DD, OSFP — these devices convert electrical signals to light and back again, riding inside a standardised mechanical housing that snaps into a front-panel cage. Their killer feature is flexibility: any module, any vendor, any switch.
The dominant architecture today runs at 800G per port, with 1.6T modules entering production in the second half of 2025. Inside each module sits a critical component: the Digital Signal Processor (DSP). The DSP's job is to compensate for the cumulative electrical loss accumulated as the signal travels from the ASIC, across PCB traces, through connectors, and into the module cage. At 100G per lane and below, this was manageable. At 200G and 224G per lane (the frontier today), the losses are severe and the DSP consumes an extraordinary amount of power to fight them.
To understand why this matters at scale: a single 51.2 Tb/s switch contains 64 ports of 800G pluggable optics. At 15W average per module, that is nearly a kilowatt just in optics power for one switch. At the cluster level, across tens of thousands of switches powering an AI training system, this becomes a budget-shattering liability. The data center optical component market surpassed $16 billion in 2025 revenue largely on the strength of 400G and 800G pluggable growth — but the efficiency wall is approaching fast.
Chapter 2: LPO — Cutting the DSP
LPO's premise is elegantly simple: remove the DSP from inside the optical module and push its compensation function back into the switch ASIC's SerDes circuitry, where it can be done more efficiently as part of the main chip. The resulting module is smaller, cooler, and cheaper — because the most power-hungry component has been excised.
The tradeoff is that LPO relies on the switch ASIC to deliver a sufficiently clean electrical signal that the module can operate without its own active error correction. This is feasible over short distances (typically under 2km in AI cluster scenarios) and with carefully engineered PCB layouts. For scale-up networking within a single rack row, the numbers are compelling.
The industry response to LPO has been striking. Over 50 networking, semiconductor, and optics companies signed the LPO Multi-Source Agreement to drive interoperability. More than 8 million 1.6T LPO ports are expected to ship by 2027. Between 2025 and 2027, LPO is projected to rapidly penetrate AI clusters and mid-sized data centers.
LPO also reshapes supply chains. By eliminating the DSP from the module, it reduces the power of Marvell and Broadcom as DSP vendors and elevates the importance of Driver/TIA chip manufacturers. This is not a minor commercial footnote — it is a multi-billion-dollar shift in value capture along the optical supply chain.
Yet LPO is, ultimately, still a pluggable technology. The optical module still lives at the board edge. The electrical signal still traverses the full PCB length. For the next generation of problems — 100+ terabit switches, XPU-to-XPU connectivity across racks — LPO is a meaningful step but not the destination.
Chapter 3: NPO — Moving Optics Onto the Board
Near-Packaged Optics is perhaps the least understood term in the interconnect vocabulary, often confused with CPO. The distinction is important. Where pluggable optics sit at the board edge and CPO sits inside the ASIC package, NPO occupies the strategic middle ground: the optical engine is mounted on the PCB in close physical proximity to the switch package — but not inside it.
The practical effect is a dramatic reduction in electrical path length. Conventional pluggable optics may require the electrical signal to traverse 100mm or more of PCB trace between the ASIC and the optical module. NPO shrinks that distance to under 25mm, slashing the insertion loss that demands power-hungry compensation and enabling bandwidth densities impossible at longer distances.
Industry observers have coined the phrase "the shoreline problem" to capture why NPO and CPO are necessary. The compute die — a GPU or switch ASIC — is dense with processing capability but physically small. Getting data bandwidth out of it is like trying to move traffic from a dense city through a bottlenecked highway system. NPO effectively widens those highways by placing the on-ramps much closer to the source.
NPO's critical advantage over CPO is serviceability. The optical engine, while mounted on-board near the package, remains accessible and replaceable. This matters enormously to data center operators who have built entire maintenance cultures around the ability to hot-swap a failed module without taking down a switch. NPO preserves that operational familiarity while delivering significant efficiency gains. Companies like Dust Photonics and LightSpeed have emerged specifically to target this architecture, recognizing it as a pragmatic bridge that hyperscalers can adopt without redesigning their entire operational model.
Chapter 4: CPO — The Integration Milestone
Co-Packaged Optics represents the first inflection point where optics and electronics cease to be separate products and become a single integrated system. In CPO, the optical engine — the laser sources, photodetectors, modulators, and waveguides — is co-packaged on the same substrate as the switch ASIC or XPU. The electrical interconnect between SerDes and optical interface shrinks from centimeters to millimeters.
The resulting physics are transformative. Broadcom's Bailly 51.2T CPO switch, described in Meta's paper at ECOC 2025, consumes approximately 5.4W per 800G of delivered bandwidth — compared to roughly 15W for a conventional 2×FR4 pluggable transceiver handling the same traffic. That is a 65% reduction in optical power, not at the component level but at the full delivered-bandwidth level.
CPO's commercial debut in 2025 was catalysed by an unmistakable signal: Nvidia announced CPO integration in its next-generation switches. At GTC 2025, Nvidia unveiled the Quantum-X (InfiniBand) and Spectrum-X (Ethernet) silicon photonics co-packaged chips. The Quantum-X switch delivers 115 Tb/s of throughput with 144 ports at 800 Gb/s each. Nvidia's Spectrum-X Photonics platform was set for Ethernet deployment in the second half of 2026. When the world's dominant AI compute platform standardises on a new interconnect architecture, the entire supply chain reorients almost immediately.
The CPO ecosystem is anchored by a handful of key players. Broadcom's 200G-per-lane CPO technology, unveiled in May 2025, represents the third generation of its silicon photonics effort. Marvell's 3D SiPho engine supports 200 Gbps electrical and optical interfaces, targeting XPU integration. Ayar Labs has taken a distinctive approach: its TeraPHY optical engine chiplets integrate directly into an ASIC's design workflow, partnering with Taiwan's Global Unichip Corp to bring CPO into advanced packaging at commercial scale.
CPO is not without friction. The integration of optics and electronics into a single package creates genuine serviceability challenges. A failed optical component in a CPO system can require replacing the entire switch ASIC assembly — a very different operational reality from sliding out a failed pluggable. Thermal management becomes more complex when lasers and digital logic share a substrate. And the tight coupling between switch chip manufacturers and optical engine suppliers creates business model tensions that the industry is still resolving.
Architecture comparison
| Architecture | Power (800G) | Serviceability | Integration depth | Standards maturity |
|---|---|---|---|---|
| Pluggable DSP | 12–20W | Hot-swap | Board edge | Fully mature |
| LPO | 6–10W | Hot-swap | Board edge | Scaling (OIF) |
| NPO | 5–8W | On-board, accessible | Near package | Emerging |
| CPO | 4–6W | Co-packaged, limited | Same substrate | Early commercial |
| OPO | <3W (est.) | Deeply integrated | On-package | Research stage |
Chapter 5: OPO — Light Becomes Native
OPO is the logical conclusion of the integration journey that CPO begins. Where CPO co-packages the optical engine with the switch ASIC on a shared substrate, OPO takes the final step: photonic components are embedded directly within the compute package itself — integrated at the chiplet or wafer level rather than assembled alongside the electronic die.
In the OPO vision, optical I/O is not an add-on or a co-designed neighbour. It is a native feature of the package architecture, as fundamental as power delivery or memory interfaces. The boundary between "compute die" and "optical interface" dissolves entirely. Data enters and exits the package as photons, with no intervening electrical signal path of any meaningful length.
The enabling technology for OPO is silicon photonics at scale. Silicon photonics uses standard CMOS fabrication processes — the same foundry infrastructure that makes electronic chips — to create optical waveguides, modulators, and photodetectors on silicon. This is the critical enabler: it means optical components can eventually be manufactured in the same processes, at the same facilities, and potentially on the same reticles as digital logic.
Ayar Labs' work on in-package Optical I/O represents one of the clearest public glimpses of what OPO eventually looks like. Their TeraPHY chiplets demonstrate optical engines integrated within an ASIC's package assembly, with electrical signals never needing to escape the package boundary to reach optical fibre. The distinction between this "in-package OIO" and traditional CPO is significant: CPO is still, at its core, a replacement strategy for switch-level pluggable optics. OPO/OIO is a compute-fabric strategy — enabling GPU-to-GPU and accelerator-to-accelerator connections over optical paths that were previously impossible without electrical bottlenecks.
TSMC's COUPE (Compact Universal Photonic Engine) roadmap provides an industrial timeline for this transition. The first generation places optical engines in OSFP connectors with 1.6 Tb/s capability. The second generation moves into CoWoS packaging with CPO at 6.4 Tb/s at the motherboard level. The third generation — the OPO destination — targets photonic integration at the package level, deeply coupled with the compute die itself. Industry momentum at OFC 2026 suggested all high-bandwidth data center interconnects will become optical within five years, with the architecture progressively approaching the OPO vision.
Why This Matters More Than Almost Anything Else
The optical interconnect evolution is not a specialist engineering story. It is one of the defining infrastructure narratives of the AI era. Every frontier AI model trained today — and every inference workload serving billions of users — depends on the ability to move data between thousands of accelerators at enormous bandwidth and vanishingly low latency. The optical interconnect is the nervous system of that infrastructure.
The power stakes are existential. Data center power consumption is growing at rates that threaten to strain national electrical grids. A 65% reduction in optical interconnect power — achievable with CPO at scale compared to today's pluggable architecture — translates to hundreds of megawatts of saved capacity across a single hyperscaler's global footprint. Over a decade of AI infrastructure buildout, this is not incremental; it is structural.
The competitive stakes are equally high. The semiconductor companies that own the leading CPO and OPO platforms — Broadcom, Marvell, and the emerging silicon photonics startups — are positioning for a winner-takes-most dynamic. CPO's tight coupling between optical engine and switch ASIC means that whoever controls the silicon controls the interconnect. This is precisely why Nvidia, not traditionally an optical company, chose to integrate CPO directly into its networking roadmap. Optical interconnect is now compute strategy.
Beyond the data center, the trajectory points toward a future where the distinction between "networking" and "computing" becomes increasingly artificial. When light flows natively within the compute package, the traditional separation between a processor and its network interface dissolves. The XPU of 2030 may not have a "network card" any more than a modern CPU has a separate "memory card." Optics will simply be how data moves — inside the package, between packages, and across the rack row.
The Destination Is Already Visible
The five-step evolution from Pluggable to OPO is not speculative. It is an engineering roadmap with known physics, measurable milestones, and committed capital. The first two steps — pluggable and LPO — are fully in production. NPO is scaling aggressively. CPO has passed the proof-of-concept threshold and is entering hyperscale deployment. OPO is the research horizon that TSMC, Ayar Labs, Broadcom, and Nvidia are all spending real money to reach.
What makes this moment particularly significant is timing. The AI compute buildout that began in 2023 and is accelerating through 2026 and beyond is locking in optical architectures for a decade or more. The hyperscalers and cloud providers writing billion-dollar purchase orders today are choosing which point on the Pluggable-to-OPO continuum they can deploy at scale, reliably, and with manageable operational complexity. Those choices will determine not just the power profiles of their data centers but the economic models for an entirely new generation of photonics companies.
Light, it turns out, was always the answer. We are simply getting better at deciding how close to the silicon it needs to live.