Inside ASML: The Product Line That Prints the Future (and Why EUV Took 30 Years)

ASML does not sell one machine. It sells three wavelengths, and each one pays for a different future.

MANISH AI | April 20, 2026 | 12 min read | Part 2 of The Machines That Build the Machines

The most important machine in AI is not a GPU. It is the scanner that prints it.

ASML’s roadmap is not a single breakthrough machine. It is a product line split by wavelength, and each wavelength still ships today. Understanding the three families, DUV, EUV Low-NA, and EUV High-NA, explains why lithography took three decades to reach 13.5 nanometers, and why the next decade is about cost per wafer, not just resolution.

EUV timeline from lab to High-NA manufacturing

Sources and Method
This article synthesizes: ASML product pages for NXE:3800E, EXE:5000, NXT:2050i; ASML investor day materials; Zeiss SMT optics notes; SPIE Advanced Lithography proceedings 2020-2025; and public statements from TSMC, Intel, Samsung, SK hynix. Pricing and timing reflect public reporting (Reuters, company releases) and ASML guidance, not private data.

Section 1: The One Equation

Everything in lithography reduces to one diffraction limit. ASML does not defeat physics, it engineers around it.

CD – critical dimension, smallest printable half-pitch

k₁ – process factor, resists, techniques, computational lithography

λ – wavelength of light, 248nm, 193nm, 13.5nm

NA – numerical aperture, how wide a cone of light the lens captures

To print smaller, you shrink λ or grow NA. DUV stayed at 193nm for 20 years by growing NA to 1.35 with immersion and driving k₁ down with multiple patterning. EUV finally changed λ to 13.5nm. High-NA now grows NA again, from 0.33 to 0.55.

Section 2: DUV — The Fleet That Still Pays the Bills

ASML ships more DUV systems than EUV every year. They are the cash engine.

System	Light	NA	Resolution	Notes
TWINSCAN XT:860N	KrF 248nm	~0.8	~110nm⁸	Mature nodes, analog, power, thick resists
TWINSCAN NXT:2000i	ArF immersion 193nm	1.35⁷	~38nm	Workhorse immersion, high productivity
TWINSCAN NXT:2050i	ArF immersion 193nm	1.35	40nm and below, improved overlay⁶	Best overlay in DUV fleet for multi-patterning

EUV did not replace DUV. Fabs optimize per layer. DUV wins on cost and maturity for middle and back-end layers. EUV wins where pitch forces it. ASML does not retire wavelengths, it layers them because economics layer.

Immersion fills the gap with water, increasing NA without changing λ

ASML does not retire products. It layers them. A modern fab still buys new NXT:2050i systems in 2026 for the 60 to 80 layers that do not need EUV.

Section 3: EUV Low-NA — Building a Star in a Box

The NXE series is why this took 30 years. ASML showed the first full-field demo in 2006, shipped the production NXE:3300B in 2013, and delivered its 100th EUV system in 2020.

The source is essentially a controlled plasma. ASML fires 50-micron tin droplets at about 300 km/hr, hits each twice with a CO2 laser, the second pulse creates a plasma at roughly 220,000°C that emits 13.5nm light⁹. Less than 2 percent of those photons survive.

Why so few? The light cannot pass through lenses, it is absorbed by glass. EUV uses 11 Zeiss mirrors in vacuum, each polished to sub-atomic roughness, each reflecting about 70 percent. Multiply eleven 0.7 reflections and the system transmission is under 2 percent.

Current system: TWINSCAN NXE:3800E

0.33 NA, 13.5nm wavelength
Designed for 2nm to 3nm class logic nodes⁴
Throughput: ASML lists 195 wafers per hour, with a roadmap to 220 wph⁵
Overlay: <1.1nm matched machine overlay, per ASML
Price: public reporting places ~$180M to $200M per system⁵

Publicly installed at leading logic foundries including TSMC, Samsung, Intel, and at Rapidus in Japan for its 2nm pilot line. The machine prints transistors about 20,000 times thinner than human hair, 195 times an hour.

Section 4: EUV High-NA — EXE:5000

Low-NA hit its resolution wall. To avoid slow, expensive EUV double patterning at 2nm-class metal, ASML grew NA.

NA increases from 0.33 to 0.55, a 67 percent jump in light cone angle¹
Resolution improves to about 8nm half-pitch in a single exposure
Optics are anamorphic, 4x magnification in one direction, 8x in the other, to manage the larger NA
ASML guides to 220 wph target throughput by 2025 for the platform
Cost: ~€350M per system per Reuters reporting³
First system delivered December 2023 per ASML, high-volume manufacturing expected 2025-2026 per company guidance²

Public allocations: Intel received the first R&D system in Oregon, SK hynix announced the industry’s first High-NA for DRAM at its Icheon site¹⁰, TSMC and Samsung have public orders for R&D and pilot lines.

Higher NA captures a wider cone, prints smaller features, needs larger reticle magnification

Why it matters: at 2nm-class and below, critical metal layers would need two Low-NA EUV exposures. High-NA does it in one, improving cycle time, yield, and edge placement control, if fabs can justify the €350M price.

Section 5: Why It Took 30 Years

Five problems had to be solved together, not in sequence:

Source power. From a few watts in the lab to >500W at intermediate focus in production, while firing 50,000 tin droplets per second
Mirrors. Zeiss had to build atomically smooth multilayer Mo/Si mirrors that survive EUV and stay flat to picometers
Contamination. Tin debris destroys mirrors. Solution: hydrogen gas cleaning, vacuum vessel, and debris mitigation
Overlay and stages. Wafers move at 700mm/s under the slit with sub-nanometer overlay. The dual-stage architecture had to evolve for vacuum
Resist. EUV photons are scarce. Chemically amplified and metal-oxide resists had to balance sensitivity with stochastic defects

The delay was structural, not a missing breakthrough. Source power without mirror lifetime was useless. Mirrors without hydrogen cleaning were useless. Stages without overlay were useless. All five subsystems had to cross manufacturability at the same time.

Section 6: How a Modern Fab Mixes Three Wavelengths

This is not a catalog, it is a layering strategy. A 2nm-class logic flow uses roughly 15 to 20 EUV layers for critical front-end and tight metal, about 60 to 80 immersion layers for middle and back-end routing, and a handful of KrF layers for the most mature levels like high-voltage I/O and power delivery. Exact mix varies by design.

System	Light	NA	Typical Use
XT:860N	KrF 248nm	~0.8	Analog, power, non-critical, >90nm features
NXT:2000i	ArFi 193nm	1.35	Multi-patterning workhorse, middle layers
NXT:2050i	ArFi 193nm	1.35	Best overlay immersion for 5nm-class multi-patterning
NXE:3800E	EUV 13.5nm	0.33	Single-exposure critical layers at 3nm and 2nm
EXE:5000	EUV 13.5nm	0.55	High-NA single exposure avoids double patterning below 2nm

Section 7: What Comes Next

The fight has shifted from pure resolution to manufacturability. The limiting factors are now photon shot noise and stochastic defects, mask pellicles that survive high power, actinic inspection to find EUV-specific mask defects, and overlay control across mixed fleets of DUV, Low-NA, and High-NA.

Next engineering battles: sources above 500W to 600W, new resist platforms with lower line-edge roughness, high-transmission pellicles, and inline metrology that can measure on-product overlay in seconds.

The next gains come from computational lithography and inline AI for defect classification, not just more photons.

ASML built a machine that turns tin into EUV light so foundries can print transistors 20,000 times thinner than hair, 200 times an hour.