How the data center networking industry is dismantling the pluggable optics paradigm — and what LPO, NPO, and CPO mean for the AI infrastructure era.
For two decades, data center networking followed a clean, serviceable architecture: a switch ASIC on a PCB, and optical transceivers plugged into cages at the front panel. Engineers loved it. Swap a bad module in seconds. Mix vendors freely. Life was good.
Then came large-scale AI training. Clusters with tens of thousands of GPUs, each demanding 800 Gbps or more of bisection bandwidth. The electrical signal now has to travel from the ASIC through the PCB, through a connector, through the transceiver's copper lanes, into a DSP chip inside the module — all before a photon is even born. Every millimeter of that journey leaks power and degrades signal integrity.
At 400G this was tolerable. At 800G, it hurts. At 1.6T, it threatens to become a fundamental wall. The industry's response has been to progressively move the optical interface closer to the ASIC — culminating in the ambition to place it inside the same package entirely.
The incumbent form factor. An optical transceiver module that snaps into a cage on the switch faceplate. Contains its own DSP for signal conditioning, clock and data recovery (CDR), forward error correction (FEC), and retiming. Mature, standardized, and deeply supported by the supply chain.
The DSP inside a pluggable module is both its superpower and its Achilles heel. It enables long electrical traces with imperfect signal quality to still produce a clean optical output — but it consumes 5–10W per module just doing that job. In a chassis with 64 ports of 400G, that's potentially 640–900W of optical DSP power alone.
Form factors like QSFP-DD (Quad Small Form-factor Double Density) and OSFP (Octal Small Form-factor Pluggable) have pushed the power envelope as far as mechanical and thermal constraints allow. The path forward requires rethinking the architecture, not iterating the form factor.
A pluggable module that removes the DSP from the transceiver entirely. The ASIC's own SerDes outputs drive the optical components directly in a "linear" signal path — no retiming, no CDR, no FEC inside the module. Signal correction is handled at the host ASIC level.
LPO is philosophically simple: if the ASIC is already capable of signal conditioning, why duplicate that function in the module? By eliminating the module's DSP, LPO cuts per-port power by roughly 30–40%, while preserving the mechanical and operational benefits of a pluggable form factor.
The catch is signal fidelity. Without a DSP to retime and correct the signal, LPO is sensitive to electrical trace quality and reach. It's ideal for intra-rack and top-of-rack connections where cable distances are short — typically under 100m for multimode, or direct-attach within a rack.
The OIF (Optical Internetworking Forum) and key players like Marvell, Credo Semiconductor, and Coherent have been instrumental in standardizing LPO interfaces. The technology is commercially available today and represents the most accessible near-term power reduction lever for hyperscalers.
The optical module is removed from the faceplate and placed physically adjacent to the switch ASIC on the PCB or on the same substrate — cutting the electrical trace from ~100mm to roughly 10–25mm. The module is no longer customer-field-swappable, but the optics remain a discrete component from the ASIC package.
NPO occupies the critical middle ground in the integration roadmap. By relocating the optical engine next to the ASIC, the electrical interconnect loss drops dramatically — enabling cleaner signals at higher baud rates without the power overhead of full DSP compensation.
Thermal management becomes more complex in NPO designs. Photonic components are sensitive to temperature, and placing them close to a high-TDP switch ASIC (often 300–500W for frontier devices) requires careful thermal isolation, heat spreaders, and potentially active cooling of the optical subassembly. This has slowed commercialization relative to LPO.
NPO is increasingly seen as a transitional architecture — valuable for the 800G generation and early 1.6T systems while CPO manufacturing matures. Intel, Broadcom, and several optical engine startups have NPO reference designs in validation.
The optical engine — lasers, modulators, photodetectors, and waveguides — is integrated directly into the same package as the switch ASIC. Electrical traces between the ASIC's SerDes and the optical interface are reduced to millimeters or less, fundamentally eliminating the high-speed electrical interconnect as a loss domain.
CPO is the endgame architecture for switch-level optical integration. By collapsing the ASIC and its optical I/O into a single package, the system eliminates the largest source of electrical power loss. Estimates suggest CPO can reduce optical I/O power by 40–60% versus equivalent pluggable solutions.
The engineering challenges are formidable. Yield and reliability of co-integrated photonic and electronic dies must meet datacenter SLAs. Laser sources must be thermally isolated and replaceable — since a failed laser should not require replacing an entire switch ASIC. The industry has converged on pluggable laser cartridges within the CPO package to address this.
Serviceability is the legitimate concern most often raised against CPO. In a pluggable system a technician swaps a bad module in under a minute. In a CPO system, a deep package-level failure could necessitate board replacement — a much higher cost event.
Broadcom demonstrated early CPO designs with its Humboldt platform. Intel has invested heavily via its integrated photonics group. Microsoft has driven CPO adoption through its Azure hardware program. Hyperscalers are expected to deploy first-generation CPO switches in production AI fabric roles by 2025–2026.
| Dimension | Pluggable | LPO | NPO | CPO |
|---|---|---|---|---|
| Optical location | Faceplate | Faceplate | Near ASIC | In package |
| DSP in module | Yes | No | Partial | No |
| Power efficiency | Baseline | +30–40% | +40–50% | +50–60% |
| Serviceability | Hot-swap | Hot-swap | Board-level | Board/package |
| Port density | Faceplate-limited | Faceplate-limited | High | Highest |
| Commercial maturity | Mature | Available | Emerging | Early |
| Primary use case | Universal | Short-reach AI fabric | 800G / early 1.6T | Next-gen AI scale |
The fabrication technology underpinning most CPO and advanced NPO designs. Silicon photonics uses standard CMOS fabs to manufacture optical waveguides, modulators, and photodetectors on a silicon substrate — enabling optical components to be co-designed with electronics using familiar toolchains. Key limitation: silicon cannot lase efficiently, so external or III-V laser sources are bonded separately.
The Optical Internetworking Forum (OIF) drives CPO and LPO interface specifications. Multi-Source Agreements (MSAs) like QSFP-DD800 and OSFP define form factors. IEEE 802.3 standards bodies define the electrical and optical parameters for 100G, 400G, 800G, and emerging 1.6T lanes — determining whether competing vendor approaches can interoperate.
Most data center optical links use PAM4 (4-level pulse amplitude modulation) for intensity-modulated direct-detect links. Coherent optics are entering the data center for distances above ~1km. At the laser level, EMLs (Electro-absorption Modulated Lasers) offer better performance for LPO linear drive scenarios, while DMLs (Directly Modulated Lasers) are lower cost for short-reach links.
CPO is enabled by the same advanced packaging trends driving chiplet-based ASICs. Universal Chiplet Interconnect Express (UCIe) defines die-to-die interfaces that could link photonic chiplets to switch ASICs. 2.5D packaging (co-placement on a silicon interposer) and 3D stacking are the physical integration approaches being explored for tight ASIC-photonic coupling.
The optical interconnect story is ultimately an AI story. Every incremental watt saved on optical I/O is a watt that can power more compute, cool a smaller facility, or reduce the energy cost per training token. At the scale of frontier model training — clusters drawing tens of megawatts — the difference between pluggable and CPO architectures could represent millions of dollars annually in operational savings.
The transition will not be abrupt. Pluggables will serve flexible, edge, and long-reach applications for many years. LPO offers the fastest near-term wins without architectural disruption. NPO serves as a practical bridge. And CPO, once manufacturing yields and packaging ecosystems mature, is the destination that the physics of high-speed interconnects has been pointing toward all along.
The chip is eating the cable. And that is, broadly speaking, a good thing.
This article covers LPO, NPO, CPO, and traditional pluggable optical interconnect technologies in the context of AI data center networking. Technologies and deployment timelines reflect the state of the industry as of mid-2025. Specifications are indicative; exact figures vary by vendor implementation and generation.