When TSMC announces its N3 process or Intel announces 18A, what is actually changing about the transistor? What does the node number mean — and why does it no longer mean what it used to? This essay explains the physics of transistor scaling from FinFET to Gate-All-Around, why Moore's Law is slowing, and what it means for AI chip design.
The "3nm" in TSMC N3 does not refer to any single physical dimension of the transistor. It is a marketing label that originated in the 1990s when it did correspond to the transistor gate length — the physical dimension of the gate that switches the transistor on and off. At that time, a "250nm process" genuinely had ~250nm gate lengths. Shrinking the gate length was the primary way to pack more transistors per unit area.
Around the 28nm–16nm transition (2011–2014), the correspondence between node name and physical gate length broke down. The competitive dynamics of the semiconductor industry incentivised foundries to use smaller node numbers as marketing claims, even as the actual physical improvements became more multidimensional — better pitch density, new transistor architectures, tighter metal spacing — rather than simple gate length reduction.
Today, "3nm" describes a process generation — a collection of manufacturing improvements that together produce higher transistor density, better power efficiency, and higher performance compared to the previous generation. The actual gate length is approximately 12 nm. The relevant physical measurements are:
| Physical metric | What it measures | Why it matters for AI chips |
|---|---|---|
| Gate pitch | Distance between adjacent transistor gates (centre-to-centre) | Determines transistor density along the gate dimension |
| Metal pitch (M0/M1) | Spacing of the finest wiring layer connecting transistors | Determines routing density and ultimately SRAM cell size |
| Cell height | Height of a standard logic cell (in track units) | Determines logic density — how many gates per mm² |
| SRAM bit cell area | Area of one 6-transistor SRAM bit cell in µm² | Determines how much on-chip cache fits per mm² of die area |
| MTr/mm² (transistors/mm²) | Total transistors per square millimetre | The headline density metric — how many logic gates per die |
A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a voltage-controlled switch. It has three terminals: the source (where current enters), the drain (where current exits), and the gate (which controls whether current flows). Between the source and drain is a thin channel of semiconductor material. The gate is separated from the channel by a thin insulating oxide layer.
When a sufficient voltage is applied to the gate, an electric field penetrates through the oxide and induces a conducting channel between source and drain — the transistor turns on. When the gate voltage is removed, the channel disappears and no current flows — the transistor turns off. This binary switching is the basis of all digital logic.
The gate length (L) is the distance between source and drain along the channel. Reducing L has three effects:
These three benefits — speed, power, density — are the classic returns of transistor scaling, and they drove the semiconductor industry for fifty years. The problem is that below approximately 5–7nm gate length, physics starts fighting back.
Until approximately 22nm (Intel, 2011), all commercial transistors used a planar architecture — the channel is a flat region at the surface of the silicon substrate, and the gate sits on top of it, separated by a thin oxide. Scaling meant making the gate shorter and the oxide thinner.
Two fundamental problems emerged as gate lengths dropped below ~20nm:
Both effects cause the same outcome: power consumption that cannot be reduced by lowering voltage, because the transistor leaks regardless of operating conditions. Planar transistors hit a physical wall at approximately 22nm gate length. A new architecture was needed.
The FinFET (Fin Field-Effect Transistor) solved the planar transistor's short-channel problem by changing the geometry of the channel. Instead of a flat channel at the silicon surface, the FinFET uses a thin vertical "fin" of silicon that protrudes from the substrate. The gate wraps around three sides of this fin.
By wrapping around three sides of the fin instead of sitting on top of a flat channel, the FinFET gate has dramatically more electrostatic control over the channel. This suppresses short-channel effects, allowing scaling to continue to approximately 5nm gate pitch. FinFETs enabled TSMC 16nm (2014) through TSMC 5nm (2020) and TSMC 4nm (2022), covering nearly a decade of Moore's Law continuation.
FinFETs have their own scaling limit. As the fin becomes narrower (to reduce footprint), quantum confinement effects change the electrical properties of the channel. Below approximately 5nm fin width, the FinFET's performance degrades. A new geometry is needed.
Gate-All-Around (GAA), also called nanosheet or nanowire transistors, wraps the gate around all four sides of the channel — not three. The channel is a horizontal sheet (or stack of sheets) of silicon, and the gate material surrounds it completely. This achieves the maximum possible electrostatic gate control, enabling continued scaling to sub-5nm pitch while maintaining acceptable leakage.
The specific implementation used by TSMC at N2 and Samsung at 3GAE is stacked nanosheets — multiple horizontal silicon nanosheets stacked vertically, with the gate surrounding each one. This not only improves electrostatic control but also increases drive current per unit footprint (by providing more channel area per device footprint), which is critical for performance at low supply voltages.
Intel's RibbonFET (in 18A and 20A) is their name for the same concept — a GAA device with stacked ribbon-like channels. The geometry differs slightly between manufacturers but the physics principle is identical: maximum gate coverage, maximum channel control.
| Process node | Foundry | Year (HVM) | Logic density (MTr/mm²) | SRAM cell (µm²) | Transistor type | Key AI chips |
|---|---|---|---|---|---|---|
| 7nm (N7) | TSMC | 2018 | ~91 | 0.027 | FinFET | A100 (TSMC 7nm) |
| 5nm (N5) | TSMC | 2020 | ~171 | 0.021 | FinFET | Apple M1, various AI chips |
| 4nm (N4) | TSMC | 2022 | ~198 | 0.019 | FinFET (improved) | H100 (TSMC 4N custom) |
| 3nm (N3E) | TSMC | 2023 | ~292 | 0.0171 | FinFET (3rd gen) | Apple M3, A17 Pro |
| 3nm (N3P) | TSMC | 2024 | ~320 | ~0.016 | FinFET (optimised) | H200, future AI GPUs |
| 2nm (N2) | TSMC | 2025–26 | ~380+ | ~0.014 | GAA nanosheet | GB300 successors, Apple A19 |
| 3GAE | Samsung | 2023 | ~145 | ~0.020 | GAA nanosheet | Samsung Exynos |
| 18A | Intel | 2025 | ~200+ | ~0.017 | GAA RibbonFET | Intel GPU successors |
A critical observation from this table: Samsung's 3GAE, despite being the world's first commercial GAA transistor (a genuine architectural advance), delivers lower density than TSMC's N3E FinFET. Transistor architecture is necessary but not sufficient — manufacturing maturity, defect density, and process optimisation determine actual density and yield. TSMC's FinFET at N3 outperforms Samsung's first-generation GAA at 3GAE because TSMC has spent years optimising its FinFET process while Samsung was first-generation on a new architecture.
The leading-edge semiconductor manufacturing market has consolidated to three credible players for nodes below 7nm: TSMC, Samsung, and Intel Foundry. Their competitive positions as of April 2026:
For AI chip designers, a node shrink translates into four concrete benefits — and the magnitude of each has changed as scaling has slowed.
| Benefit | Mechanism | N7→N4 (historical) | N4→N2 (current gen) | AI chip implication |
|---|---|---|---|---|
| More transistors per mm² | Smaller devices, tighter pitch | ~2.2× density | ~1.9× density | More tensor cores, more SRAM per die area |
| Lower power per operation | Lower capacitance per transistor | ~25–30% reduction | ~15–20% reduction | More tokens per watt; lower cooling requirements |
| Higher frequency at same power | Faster transistor switching | ~10–15% gain | ~5–10% gain | Modest clock frequency improvement |
| More die area for same cost | Smaller die for same function | Significant | Diminishing | Cost reduction per unit compute slower than historically |
The key trend: the gains per node are real but diminishing. N7 to N4 delivered approximately 2.2× transistor density, ~30% power reduction, and ~15% frequency gain. N4 to N2 is projected to deliver ~1.9× density, ~20% power reduction, and ~8% frequency gain. The returns are still positive — every generation of AI chip benefits from the node advance — but the magnitude of improvement per generation is smaller than it was in the FinFET scaling era.
Moore's Law — the observation that transistor density doubles approximately every two years — has not ended, but it has slowed materially. The two-year cadence has stretched to three to four years for density doublings, and the cost per transistor has stopped falling (it actually increased at some nodes).
The causes are physical and economic:
The industry's response has been to invest in packaging innovation as an alternative to planar scaling. Instead of making transistors smaller, connect more chiplets together with shorter, denser interconnects. HBM, CoWoS, EMIB, TSMC SoIC, and Intel's 3D Foveros are all variants of this strategy — achieving system-level performance improvements through better integration rather than better individual transistors.
For AI chip designers, the slowdown of transistor scaling creates a specific set of constraints and opportunities through 2030:
The "free lunch" of Moore's Law — where every two years you got twice as much compute for the same cost — is over for AI chip design. The next generation of performance improvement requires architectural creativity: better packaging (chiplets, advanced 3D integration), smarter on-chip memory management, and workload-specific silicon design. The transistor is still improving. It is improving more slowly, more expensively, and with smaller returns per generation. That changes the calculus for every AI chip programme launched after 2024.