Technical portfolio · invention-led systems work

Architecture for AI infrastructure with runtime depth.

I work on memory movement, control planes, inference runtime behavior, CUDA-adjacent systems questions, and patent-backed infrastructure ideas to make large models more legible, schedulable, and deployable.

Runtime systems Memory orchestration CUDA / GPU systems Patents + public artifacts

Explore featured work Browse writings Patent record

52 U.S. patents / applications spanning systems, telemetry, memory policy, and AI infrastructure.

25 India filings in 2026 across wired residency, orchestration, control planes, inference systems, and KV-cache hardware.

Machine-near Board bring-up, boot paths, firmware, runtime behavior, and system design under hard constraints.

Current operating surface

Memory, runtime, and infrastructure behavior as one system.

The recurring thread: fewer wasted bytes moved, clearer control surfaces, and infra decisions that preserve useful work under load.

SRAM Tier Wired residency · hot state lowest latency

HBM Working Set decode bandwidth · active tensors primary path

DRAM Spill staging, queues, host coordination policy managed

NVMe Backing cold state · deferred hydration bounded transfer

Runtime Core Policy & Orchestration

Admission, routing, execution paths, and memory movement under explicit system constraints.

Prefill Surface hydration · staging · routing prep queued

Decode Path token step · KV movement · control active

Telemetry Loop signals, throttles, runtime state observed

Queues bounded admission windows

Policy memory-aware execution control

Signals telemetry closes the loop

Why this site exists

Public artifacts for architecture-heavy systems work.

This site pulls together essays, patents, repositories, and technical microsurfaces around one recurring concern: how large systems behave under load, constraint, and imperfect control.

The goal is simple: make the work inspectable. Instead of summarizing from a distance, it links to the public artifacts where the reasoning, structure, and invention record are visible.

Patents Invention-led work across control planes, memory hierarchy, device systems, and inference.

Writings Long-form technical essays with full systems arguments, not just polished summaries.

Build depth Board bring-up, firmware paths, runtime abstractions, CUDA study work, and infra reasoning.

Systems foundations

Machine-near background that still shapes runtime thinking.

Board Bring-Up

ARM and MIPS platform bring-up, early initialization, and reasoning about systems before the full stack exists.

Firmware & Boot

Recovery paths, initialization order, partial-liveness debugging, and hard causality under tight constraints.

Why It Matters

The same discipline maps cleanly to AI infra: failure boundaries, resource pressure, orchestration, and memory behavior.

Featured work

Flagship systems work, public artifacts, and invention-backed infrastructure ideas.

A fast read on the strongest artifacts: what problem is being attacked, what was built or argued, and why the systems angle matters.

Runtime-first Scheduling, memory behavior, and execution control are treated as first-class product surfaces.

Public proof Repositories, essays, and microsites make the reasoning legible instead of burying it behind claims.

Patent-backed ideas Several artifacts connect directly to filed infrastructure concepts around orchestration, residency, and control planes.

Writing

Technical essays with room for the full systems argument.

The writing is where ideas get enough air: decode bottlenecks, memory hierarchy, cluster reliability, CUDA/GPU behavior, and architecture-level arguments that do not fit in a project blurb.

Editorial layer

Serious essays, not filler blog content.

The writings section is intentionally treated more like a publication surface than a changelog. The essays exist to make technical reasoning legible, preserve nuance, and turn prototype-level ideas into public arguments others can evaluate.

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Patent record

Granted patents, active filings, and a visible invention engine for infrastructure systems.

Named inventor across device virtualization, remote testing, telemetry, operating systems, AI infrastructure, GPU runtimes, memory hierarchies, accelerator systems, and orchestration surfaces.

52 U.S. patents / applications

30 India filings in 2026

69+ Total applications tracked on site

Across Inference systems, memory control, telemetry, and runtime architecture

Selected filing

Hardware-enforced on-chip memory residency

Extends a wired-entry idea into the memory hierarchy so hot inference state can remain on chip under explicit runtime control.

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Selected filing

Cross-layer gray failure orchestration

Moves cluster reliability beyond restart logic toward throughput-preserving control decisions under partial degradation.

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Selected filing

Compiler-emitted memory intent

Treats placement, migration, retention, and spill policy as structured intent rather than something hardware has to infer late.

Open the filing

Open full patent record

Year	Patent No.	Title

Contact

Open to architecture-heavy conversations in AI infrastructure, runtimes, and memory systems.

If you are building around inference efficiency, runtime policy, systems architecture, or invention-led infrastructure work, this is the right surface to start from.

GitHub Patent record Writings