Board Bring-Up
ARM and MIPS platform bring-up, early initialization, device-level quirks, and reasoning through systems before the full software stack exists.
Portfolio Hub
Manish KL
A portfolio of systems, patents, AI infrastructure, and architecture-driven technical products.
Central index for live project microsites, selected repositories, and invention-led technical work across runtime systems, infrastructure design, explainable platforms, and architecture-heavy product execution.
Systems
AI Infrastructure
Patents
Writings
CUDA / GPU
Open Source
Featured patent
Context Region Orchestration
Long-context inference microsite
Featured invention
WDC-Engine
Semantic deduplication and shared execution for enterprise multi-agent systems
Featured platform
MHC Atlas OS
Explainable prioritization
Featured concept
SRMIC
Memory-bound inference
Featured product
Mobile Agent Control
Mobile control plane for coding agents
Featured study library
PMPP CUDA Study
150 CUDA examples and optimization studies
Featured open source
vOrchestrate
Predictive weight residency orchestration for LLM inference
Featured tool
ChromeLens
Systems-grade web performance telemetry
Systems Foundations
Low-level systems work that still shapes how I think about infrastructure, runtime reliability, and machine-near control.
Before the current focus on AI infrastructure, patents, and architecture-led technical systems, much of my work lived close to the machine: ARM and MIPS board bring-up, firmware workflows, boot paths, U-Boot, and hardware-near debugging. This machine-near background provides a unique vantage point on system behavior—one where "software" only exists after a sequence of deterministic hardware gates and initialization logic. That foundation still shapes how I think about runtime reliability, control surfaces, and infrastructure behavior under real constraints, ensuring that even high-level abstractions remain grounded in physical machine realities.
Firmware & Boot Paths
Bootloader-centric workflows, U-Boot, initialization order, recovery paths, and low-level debugging when the machine is only partially alive.
Why It Still Matters
The same discipline maps directly to AI infrastructure, runtime control, fleet reliability, and machine-level platform engineering.
That low-level systems foundation still informs the architecture and execution model behind the work featured across this portfolio.
Featured work
The primary live sites and most important public technical artifacts.
Featured cards act as the main entry points into the strongest project pages, designed to scale cleanly as additional microsites are added.
Patent / ML Systems / Long-Context Inference
Predictive Context Region Orchestration
Runtime orchestration for long-context inference using per-region attention and residency control, predictive prefetch, reversible demotion, and coherence-protected generation.
A publication-grade patent microsite presenting the dual-state controller, region scoring model, multi-state demotion ladder, predictive promotion path, and coherence-veto guardrail.
Patent / Enterprise AI / Multi-Agent Systems
WDC-Engine
Semantic deduplication and shared execution for enterprise multi-agent systems.
WDC-Engine is a middleware architecture that detects semantically equivalent or near-equivalent tasks generated by multiple AI agents, collapses them into a single live execution, and fans out the result to all subscribers. The goal is to reduce redundant database, API, and compute work before it ever hits backend infrastructure.
Technical Microsite · Local Prototype · Patent Work
Open-source Platform / Computational Biology / Explainable Systems
MHC Atlas OS
An explainable, runtime-agnostic platform for structure-guided experimental prioritization.
A technical microsite for an architecture-led platform built around structure-derived signals, policy-governed workflows, and readable outputs.
Systems Architecture / AI Infrastructure / Memory-Bound Inference
SRMIC
A bounded working-set model for distributed SRAM-backed decode acceleration.
A memory-centric inference concept exploring SRAM residency, regional fabric design, and decode-path efficiency for large-model serving.
CUDA Study Library / GPU Programming / Parallel Computing
PMPP CUDA Study
A structured CUDA study repository with 150 examples across core PMPP-style patterns and advanced studies.
A technical GitHub Pages microsite and companion repository for learning CUDA systematically, from basic kernels through reduction, scan, tiling, and practical ML-oriented operators.
Open Source / LLM Inference / Memory Orchestration
vOrchestrate
A Python library for predictive multi-tier weight residency orchestration across HBM, DRAM, and NVMe during transformer inference.
Implements a seven-state residency controller, composite block scoring, accuracy guardrails, and an async prefetch pipeline for memory-efficient large-model inference.
Systems Architecture / Web Performance / Telemetry
ChromeLens
A fleet-wide deterministic CDP telemetry engine for systems-grade web performance analysis.
Leverages Chrome DevTools Protocol tracing to automate deep hardware bottleneck extraction across massive monolithic web platforms, identifying V8 locking and interaction hydration penalties.
Writings
Technical essays and long-form writing with room for the full systems argument.
A central library for deeper explanations, project essays, and patent-adjacent technical writing that reads more like a serious article than a landing page.
Hardware-enforced on-chip memory residency
A long-form explainer on SRAM residency, bandwidth bottlenecks in autoregressive inference, and why a wired hardware primitive matters.
Read the essay →Stopping local agents from doing the same work twice
A systems write-up on shared execution units, bounded admission windows, and middleware-layer deduplication in local multi-agent runtimes.
Read the essay →HBM Fragmentation Guard
Confidence-gated residency control, thrash budgets, and safe-window compaction for AI accelerator memory management.
Read the essay →Patent record
Patent work organized as a browsable record with direct access to the full list.
A linked summary of granted patents and recent filings, with the full record available on a dedicated page.
Patents / full record
Patents & Inventions
Named inventor across device virtualization, remote testing, telemetry, operating systems, AI infrastructure, GPU runtimes, memory hierarchies, and accelerator systems.
52
U.S. patents / applications
22
India filings in 2026
61+
Total applications
Selected U.S. patents
View section| Patent No. | Title |
|---|---|
| US 10,698,310 B2 | Regional device profiling systems |
| US 10,643,638 B2 | Remote capture of live session interactions |
| US 10,476,140 B2 | Distributed real-device performance testing |
| US 10,245,771 B2 | Multi-tenant mobile-device session isolation architectures |
| US 10,154,221 B2 | Adaptive network condition simulation for real-device testing environments |
| US 10,088,934 B2 | Cluster-based device assignment |
Recent India filings
View section| Application No. | Title |
|---|---|
| 202641043359 | SYSTEM AND METHOD FOR HARDWARE-ENFORCED WIRED ON-CHIP VOLATILE MEMORY RESIDENCY WITH EXPLICIT BIND-RELEASE SEMANTICS FOR NEURAL NETWORK INFERENCE ACCELERATORS |
| 202641043858 | System and Method for Cross-Layer Gray Failure Detection, Propagation-Risk Estimation, and Throughput-Preserving Orchestration in AI Compute Clusters |
| 202641045347 | System and Method for Hardware-Resident Memory-Centric Orchestration of Multi-Tier Data Movement for Artificial Intelligence Compute Fabrics |
| 202641045998 | System and Method for Compiler-Emitted Memory Intent Intermediate Representation for Multi-Tier Artificial Intelligence Memory Orchestration |
| 202641042337 | Semantic Deduplication and Shared Execution of Agent-Generated Enterprise Tasks |
| 202641041011 | Deterministic Staged Context Orchestration for Large Scale Multimodal AI Reasoning Systems |
| All filings | Open the full India filings section for the complete list and dates. |
Selected projects and repositories
Secondary entry points across the broader body of technical work.
Grouped by repository themes and project families so the portfolio reads as a coherent body of work rather than a loose list of links.
Inference and state-management systems
Architecture-heavy work spanning inference state, execution control, system boundaries, and infrastructure design.
View repositories →Agent and runtime execution models
Runtime abstraction, orchestration paths, policy-aware execution, and system-level process design.
View runtime work →Mobile Agent Control
A vendor-neutral mobile control plane for terminal-native coding agents, with Gemini CLI as the flagship integration.
View published site →Explainable platforms
Projects treating explainability, readable outputs, and engineering discipline as core product attributes.
View MHC Atlas OS →Publication-oriented invention work
Microsites and invention materials presented with technical seriousness, including the context-region orchestration patent.
View patent repo →vOrchestrate
Predictive multi-tier weight residency orchestration for transformer inference, with state-aware scoring and async prefetch.
View vOrchestrate →Areas of work
The portfolio in a small number of technical themes.
Systems Architecture
Execution models, state handling, infrastructure design, and architecture-led systems composition.
AI Infrastructure
Runtime behavior, orchestration, memory systems, and inference-adjacent technical design.
Patents & Invention
Invention-focused work framed as serious technical material rather than marketing collateral.
Open-source Platforms
Architecture-heavy platform work emphasizing explainability, governance, and product discipline.
Runtime & Performance
Performance, execution control, lower-level engineering, and technically rigorous tooling.
About / approach
Architecture-first, invention-aware, and technically disciplined.
The work collected here is organized around serious technical construction: systems thinking, architecture-led design, invention-oriented execution, and product work grounded in engineering detail.
The goal is not breadth for its own sake — it is to build coherent technical artifacts across platforms, infrastructure ideas, runtime systems, patents, and open-source projects that reward careful evaluation.
My background includes low-level board bring-up, firmware, and bootloader-centric debugging across ARM and MIPS—a foundation that still informs how I think about runtime systems, control planes, and infrastructure reliability.
Highlights
Selected signals across the portfolio.
Publication-grade GitHub Pages sites for patents, platform architectures, and technical system showcases.
Open technical platforms positioned around architecture, governance, and readable outputs.
Patent-oriented work treating system architecture and execution behavior as first-class technical material.
Interest in runtime systems, memory behavior, orchestration discipline, and technically credible surfaces.
Contact
For serious technical discussion and architecture-oriented collaboration.
For technical discussion, platform work, invention-oriented collaboration, or related engineering conversations, reach out through the channels below.