M MAN\SH AI
⬡ Deep Dive · Electronics · AI Infrastructure

The $1 Component That Every AI Server Desperately Needs

Inside the multilayer ceramic capacitor — a fingernail-sized passive component made of ancient minerals, manufactured in the billions, and silently responsible for keeping the world's most powerful chips alive.

Published June 2026
Reading time ~18 min
Topic MLCC · Power Integrity · AI Hardware

The Invisible Foundation of Artificial Intelligence

A single NVIDIA H100 GPU costs $30,000. The rack that houses it costs more still. The data center cooling system, the fiber network, the custom silicon — billions of dollars of engineering stacked together. But holding it all together, hidden beneath every processor, is a component that costs less than a cup of coffee.

The Multilayer Ceramic Capacitor, or MLCC, is an unglamorous rectangle of ceramic and metal typically the size of a grain of sand. It is boring by design. It does one thing: it smooths out electrical noise on power lines. But that one thing — voltage stabilization — is existential for modern computing.

Remove the MLCCs from an AI server and the chips inside would crash within nanoseconds. They cannot tolerate power fluctuations that the human eye would never detect. MLCCs absorb and release charge so fast and so precisely that they effectively make each chip's power supply appear perfect — a constant, calm, unwavering voltage — in a physical environment that is anything but.

"Every AI server contains tens of thousands of MLCCs. A single H100 GPU board alone can carry over 10,000 of them. They are not optional. They are as fundamental as the transistors they protect."

~10KMLCCs per H100 server board
4T+Units manufactured per year globally
<$1Typical unit cost
1nF–100µFCapacitance range
<1nsResponse time
125°C+Max operating temp

What Exactly Is an MLCC?

A capacitor is a device that stores electrical charge between two conductive plates separated by an insulating material (the dielectric). The more layers, the more surface area, the more capacitance. The MLCC simply takes this principle and stacks hundreds of ceramic-and-metal layers into a monolithic block the size of a sesame seed.

FIG 1 Exploded Anatomy of a Multilayer Ceramic Capacitor
CROSS-SECTION VIEW — NOT TO SCALE TERM TERM ELECTRODE Ceramic Dielectric (BaTiO₃ based) Inner Electrode (Nickel, Palladium) End Terminal (NiSnCu plated) 100–1000+ layers stacked ASSEMBLED 0402 package shown sintered 1.0mm × 0.5mm (0402)
Fig 1. Exploded cross-section of an MLCC showing ceramic dielectric layers interleaved with inner metal electrodes, terminated at both ends. Hundreds to over a thousand such layers are stacked in a production component.

The Ceramic Dielectric

The insulating material between the plates is the heart of the MLCC. It is almost always a barium titanate (BaTiO₃)-based ceramic. The reason is remarkable: barium titanate is a ferroelectric material, meaning it has a spontaneous electric polarization that can be reversed. This property gives it a dielectric constant many thousands of times higher than air, allowing enormous capacitance in a tiny volume.

The ceramic is deposited as slurry, dried into thin sheets (sometimes just 1–3 micrometers thick), and then stacked with printed metal electrode layers in between. The entire stack is compressed and fired in kilns at around 1,200°C — a process called sintering — which fuses everything into a single monolithic block.

EIA Size Codes

EIA CodeSize (mm)Typical UseNotes
02010.6 × 0.3Mobile SoCs, fine-pitch BGARequires advanced pick-and-place
04021.0 × 0.5Consumer electronics, AI GPUsMost common in AI server boards
06031.6 × 0.8General purpose, decouplingEasier to handle and inspect
08052.0 × 1.25Power conversion, bulk filteringHigher capacitance available
12063.2 × 1.6High-voltage, power supplyUsed in VRM input filtering
12103.2 × 2.5Bulk capacitance near power railsCan reach 100µF+

Why Chips Need Voltage Stabilization

A modern GPU like the H100 contains over 80 billion transistors. Each transistor is a tiny switch that toggles between on and off billions of times per second. Every time billions of transistors switch simultaneously, they demand a sudden surge of current from the power supply — a phenomenon called a current transient.

The power supply (voltage regulator module, or VRM) cannot respond instantly. Its inductance and physical distance mean current delivery lags behind demand by tens or hundreds of nanoseconds. During that lag, voltage droops. If voltage droops below the chip's minimum operating threshold — even for a few nanoseconds — the chip makes computation errors or crashes entirely.

FIG 2 Voltage Transient Response: Without vs. With MLCC Decoupling
WITHOUT DECOUPLING CAPACITORS TIME (nanoseconds) → VOLTAGE → VDD Vmin DROOP ~150mV Switching event FAULT ZONE WITH MLCC DECOUPLING TIME (nanoseconds) → VDD Vmin ~30mV ripple only Switching event ← MLCCs discharge
Fig 2. A current transient (chip switching event) causes a severe voltage droop without MLCCs, potentially entering the fault zone. With MLCC decoupling, local charge is instantly supplied, limiting the droop to a safe margin above Vmin.

MLCCs solve this by acting as local charge reservoirs placed within millimeters of the chip. When the chip demands current, the MLCC discharges instantly — far faster than the VRM can respond. When the transient is over, the VRM recharges the MLCC for the next event. The chip sees a smooth, stable voltage. The MLCC absorbs all the violence of the switching event.

⚡ Key Physics: Why Ceramics Are So Fast

Electrolytic capacitors (the cylindrical ones in older electronics) use a liquid electrolyte and have significant parasitic inductance and resistance. They are good for bulk energy storage but too slow for high-frequency transients.

MLCC's ceramic dielectric, combined with its extremely short internal current paths (the layers are micrometers thick), gives it an Equivalent Series Inductance (ESL) in the range of 0.5–2 nanohenries. This is what makes them effective at hundreds of MHz — exactly the frequency range of modern processor switching events.

Where MLCCs Live Inside an AI Server

An AI server is not one computing device — it is a symphony of interdependent subsystems, each with its own power integrity demands. MLCCs appear at every layer, in different sizes, capacitances, and dielectric classes.

FIG 3 AI Server Architecture — MLCC Deployment Zones
AC/DC PSU 3kW+ input 48V Bus Distribution rail VRM / POL Voltage Regulator Module H100 / A100 GPU 80B transistors · 700W TDP SM SM SM SM SM SM ●●●●●●●●●●●●●●●●●●● MLCC ARRAY 2000–5000 decoupling caps placed ≤5mm from die edge HBM3 80GB Stack NVLink 900 GB/s CPU Host 2× EPYC / Xeon DRAM DDR5 NIC 400GbE PCIe Gen5 Fabric MLCC placement zone GPU / Accelerator Power regulation TOTAL MLCC COUNT PER SERVER NODE (estimated): GPU dice: 5,000–10,000 VRM/power: 2,000–4,000 Memory/NIC/CPU: 3,000–6,000 TOTAL: ~10,000–20,000 Per rack (8× GPU nodes + networking): 100,000 – 200,000+ MLCCs
Fig 3. Annotated AI server block diagram showing MLCC placement zones (red dots) across every major subsystem. The density is highest around GPU dice and voltage regulators.

Zone 1: GPU Die Decoupling

The densest concentration of MLCCs in any AI server is directly around the GPU package. These capacitors — often in 0402 or 0201 packages — are placed in a ring within 5mm of the die edge, and sometimes even in the package substrate itself (embedded capacitors). Their job: supply instantaneous current during compute bursts when thousands of CUDA cores activate simultaneously.

Zone 2: Voltage Regulator Modules (VRM)

The VRM converts 48V or 12V supply rail voltage down to the GPU's core voltage (typically 0.8–1.1V). This conversion is noisy. Large MLCCs (0805, 1206) on the input and output of the switching converter filter the high-frequency switching noise that would otherwise propagate to the GPU.

Zone 3: Memory Stacks (HBM / GDDR)

HBM3 memory in GPUs like H100 runs at extremely high bandwidth (3.35 TB/s per chip). The memory interface is sensitive to noise. MLCCs are placed densely around each HBM stack to maintain clean power at the memory I/O circuits.

Zone 4: High-Speed SerDes / NVLink / PCIe

NVLink (used for GPU-to-GPU communication at 900 GB/s) and PCIe Gen5 interfaces contain serializer/deserializer (SerDes) circuits running at tens of gigabits per second. These are noise-intolerant. MLCCs in the power domains of these circuits prevent bit errors from power supply noise.

Zone 5: CPU and System Memory

The host CPU(s) — typically dual AMD EPYC or Intel Xeon — have their own extensive MLCC populations. Modern server CPUs with up to 96 cores switching at multi-GHz frequencies create substantial transients. DDR5 memory requires tight voltage regulation (1.1V ±2%), enforced by capacitor arrays along each DIMM slot.

Class I vs. Class II: The Important Distinction

Not all MLCCs are created equal. Their dielectric material determines their electrical behavior — and engineers must choose carefully based on where in the circuit the capacitor lives.

FIG 4 Class I vs Class II MLCC — Properties Comparison
CLASS I — C0G / NP0 TEMPERATURE STABILITY ★★★★★ CAPACITANCE DENSITY ★★☆☆☆ VOLTAGE LINEARITY ★★★★★ FREQUENCY RESPONSE ★★★★★ COST EFFICIENCY ★★☆☆☆ BEST FOR: Timing circuits, oscillators, RF filters, precision analog. Stable across temperature & voltage. CLASS II — X7R / X5R / Y5V TEMPERATURE STABILITY ★★★☆☆ CAPACITANCE DENSITY ★★★★★ VOLTAGE LINEARITY ★★★☆☆ FREQUENCY RESPONSE ★★★★☆ COST EFFICIENCY ★★★★★ BEST FOR: Bulk and mid-frequency decoupling on AI chips, DDR5, PCIe. High capacitance per unit volume.
Fig 4. Class I (C0G/NP0) MLCCs offer near-perfect stability but low capacitance density. Class II (X7R, X5R) sacrifice some stability for up to 10× more capacitance per volume — essential for decoupling duty near power-hungry AI chips.
Dielectric CodeTemp RangeCapacitance VariationTypical C RangePrimary AI Server Use
C0G (NP0)−55 to +125°C±30 ppm/°C (negligible)1pF – 100nFOscillators, PLL filters, RF bypass
X7R−55 to +125°C±15%1nF – 47µFGeneral decoupling near CPUs/GPUs
X5R−55 to +85°C±15%1µF – 100µFHigh-cap bulk decoupling on PCB
Y5V−30 to +85°C+22%/−82%Up to 470µFRare in servers; high cap, poor stability

The Three-Stage Power Delivery Hierarchy

Engineers do not place one type of capacitor and call it done. Modern AI chip power delivery uses a three-stage capacitor hierarchy, each stage handling a different frequency range of power transients:

FIG 5 Power Delivery Network Capacitor Hierarchy
STAGE 1 — BULK Electrolytic/Polymer VALUE 100µF – 10mF HANDLES UP TO 10–100 kHz PLACED AT VRM output STAGE 2 — MID-FREQ MLCC X7R · 0402 / 0603 PCB-mounted VALUE 1µF – 100µF HANDLES UP TO 1–100 MHz PLACED AT ≤5mm from chip STAGE 3 — HI-FREQ MLCC ●●●●●●●●●●● C0G · 0201/0402 in-package / substrate VALUE 1nF – 10µF HANDLES UP TO 100 MHz – 5 GHz PLACED AT On/in die package higher freq higher freq FREQUENCY COVERAGE MAP BULK: 0–100kHz MID-FREQ MLCC: 100kHz–100MHz HI-FREQ MLCC: 100MHz–5GHz CHARGE FLOW TIMING DURING A TRANSIENT EVENT 0ns 10ns 100ns 1µs 10µs+ HI-FREQ MLCC responds MID-FREQ MLCC responds BULK responds VRM takes over
Fig 5. The three-stage PDN hierarchy. High-frequency MLCCs (C0G, on/near package) respond in under 1ns. Mid-frequency X7R MLCCs on the PCB handle the 10–100ns window. Bulk capacitors bridge the gap until the VRM control loop stabilizes.

The Geopolitics of a Grain of Sand

The MLCC industry is one of the most concentrated in all of electronics. Three Japanese companies — Murata, TDK/EPCOS, and Taiyo Yuden — control approximately 70% of global MLCC production. South Korean Samsung Electro-Mechanics and Taiwanese Yageo are also major players. There are almost no significant Western manufacturers.

FIG 6 Global MLCC Supply Chain Map
North America Europe Japan S.Korea Taiwan China MUR ~36% Murata Mfg. TDK ~14% TY ~10% SEM Samsung EM ~11% YAG Yageo ~8% DC AWS US AI Data Centers EU RAW MATERIAL SOURCES BaTiO₃ (Ceramic): Barium from USA, China, India. Titanium from China, Australia Ni Electrodes: Indonesia, Philippines, Russia (~40%) Palladium (legacy): South Africa, Russia (~75% global supply) Major manufacturer Supply flow
Fig 6. Global MLCC supply chain. ~70% of production is concentrated in Japan (Murata, TDK, Taiyo Yuden), with key raw material inputs from Southeast Asia, Australia, and Russia — a geopolitical concentration that creates supply chain risk.

The concentration of production in Japan creates a genuine supply chain risk that the AI industry is only beginning to grapple with. In 2018, a severe MLCC shortage drove prices up 400–600% on certain components. Automotive and consumer electronics companies scrambled to secure supply. AI server manufacturers are now their own kind of mega-customer, ordering MLCCs in quantities previously unheard of for a single end-use application.

"A single NVIDIA DGX H100 system contains 8 GPUs. Each GPU board alone may require 10,000+ MLCCs. One DGX rack — 100,000+ capacitors. A hyperscale cluster of 100,000 GPUs? You're looking at over a billion MLCCs."

What Happens When MLCCs Fail

Despite their simplicity, MLCCs can fail — and when they do in an AI server, the results can be catastrophic or silent and slow.

FIG 7 MLCC Failure Modes and Consequences
FLEX CRACKING PCB flex stress during rework or thermal cycling CONSEQUENCE: Short circuit → board damage or thermal runaway DELAMINATION Layer separation from thermal shock (reflow too fast) CONSEQUENCE: Open circuit → loss of decoupling, intermittent errors DIELECTRIC AGING Capacitance degrades ~2–5%/decade hour (Class II only) CONSEQUENCE: Gradual drift → reduced noise immunity over server lifetime SOLDER FATIGUE Thermal expansion mismatch (CTE) after ~10K cycles CONSEQUENCE: Intermittent → hard to diagnose, random GPU errors MLCC RELIABILITY IN AI SERVERS MTBF (typical server grade) 10⁹ – 10¹¹ hours Failure rate (FIT, per 10⁹ hours) 0.1 – 1 FIT With 10,000 MLCCs per board 1–10 failures per year
Fig 7. Four primary MLCC failure modes in AI servers. At 10,000+ MLCCs per board, even a 0.01% failure rate translates to meaningful board-level risk over a 5-year server lifetime.

The Future of On-Die Power Delivery

The trends in AI computing are pushing power delivery to its limits. The H100 consumes 700W. The next-generation Blackwell B200 exceeds 1,000W. Future chips may demand 2,000W or more. At these power levels, even the best PCB-mounted MLCCs are not fast enough — the inductance of the board traces and package connections creates voltage droop that cannot be filtered away.

Embedded Die Capacitors

Chip makers are exploring integrating capacitors directly into the package substrate — and eventually into the silicon itself. Deep Trench Capacitors (DTCs) are etched into silicon wafers, creating capacitance with near-zero inductance. Intel has announced its "PowerVia" backside power delivery technology, which places power delivery on the back of the die, allowing capacitors to be placed directly below the active transistors.

Advanced Packaging Integration

In 2.5D and 3D IC packaging (used in HBM-on-GPU configurations), MLCCs are now being embedded directly into the interposer — the silicon or organic bridge connecting the chips. This reduces the distance from capacitor to transistor from millimeters to micrometers, dramatically improving transient response.

FIG 8 Evolution of Capacitor Integration — PCB → Package → Die
2005 PCB-mounted only CPU/GPU ~10mm distance 2020–2025 Package-embedded substrate MLCCs GPU/CPU DIE ~1mm distance 2026+ Backside / Die-embedded GPU DIE (active transistors) Deep Trench Capacitors (DTC) integrated on die backside <0.01mm distance evolution evolution
Fig 8. The trajectory of capacitor integration: from discrete PCB-mounted MLCCs (~10mm from die) in the 2000s, to package-embedded capacitors (~1mm) today, to die-integrated deep trench capacitors (sub-0.1mm) emerging now. Each step dramatically reduces parasitic inductance and response latency.

The Humble Gatekeeper of the AI Age

There is something almost philosophical about the MLCC. In a world obsessed with the most advanced, most expensive, most complex technology ever built, the thing that keeps it all running is a grain-of-sand-sized block of ancient ceramic — barium, titanium, oxygen — sintered at 1,200 degrees and placed by the thousands with sub-millimeter precision.

The AI revolution is not only built on transformer architectures and massive datasets and GPU compute. It is built on meticulous, unglamorous power integrity engineering. Every token generated by a large language model was enabled by thousands of tiny ceramic capacitors quietly absorbing voltage transients nobody can see, operating at speeds faster than any mechanical system can contemplate, for years at a time, without complaint.

They are not magic. They are just physics, relentlessly applied. And the next time someone tells you the future runs on silicon, you can tell them it also runs on barium titanate — and a whole lot of it.

"The most important component in an AI server is not the GPU. It is the capacitor that makes sure the GPU can do its job without flinching."

4TMLCCs produced per year — equivalent to 500 per human on Earth
~70%Global market share held by 3 Japanese companies
1,200°CSintering temperature — hotter than volcanic lava
<1nsResponse time — 100× faster than the fastest camera shutter