The Substrate Layer

What a Substrate Actually Does

Every semiconductor die that leaves a fab is essentially a tiny, fragile slab of silicon with hundreds or thousands of microscopic electrical contacts on its surface. That die cannot directly plug into a printed circuit board — the pitches are incompatible, the die is mechanically vulnerable, and the thermal and electrical characteristics require careful management. The substrate is the engineered intermediary that solves all of these problems simultaneously.

The substrate performs four distinct engineering functions simultaneously. First, pitch fan-out: a modern AI chip die may have hundreds of thousands of I/O connections at pitches as fine as 40–100 microns, while a PCB operates at pitches of 500–1000 microns or wider. The substrate fans out this extreme density into something the PCB can receive.

Second, signal integrity: high-speed electrical signals require precisely controlled impedance, minimal crosstalk, and defined return current paths — all managed through the substrate's dielectric properties, copper geometry, and layer stack design.

Third, power delivery: modern chips consume hundreds of watts that must be distributed uniformly across the die at very low noise. The substrate's power and ground planes are critical to maintaining clean supply voltage. Fourth, mechanical and thermal: the substrate physically protects the die, manages coefficients of thermal expansion (CTE) mismatch between silicon and board, and provides a path for heat to flow toward the heatspreader.

Organic Substrates: ABF and BT

The overwhelming majority of semiconductor packages today use organic substrates — multi-layer laminates built from resin-based dielectric materials with copper conductors. Two families dominate: ABF (Ajinomoto Build-up Film) and BT (Bismaleimide Triazine). Understanding the difference between them is essential to understanding modern substrate supply dynamics.

ABF: the material powering advanced computing

Ajinomoto Build-up Film is a photosensitive resin film developed by — yes — the Japanese food company Ajinomoto, which diversified into specialty chemicals. ABF is applied as a thin film over copper conductor layers and then laser-ablated or photolithographically patterned to create blind vias and fine-line traces. Its key property: the material can support trace/space linewidths down to 2µm and below, enabling the extreme routing density required by modern CPUs, GPUs, and AI accelerators.

Every major computing substrate today — Intel CPUs, AMD EPYC, NVIDIA A100/H100/H200, Apple M-series, Qualcomm Snapdragon, Broadcom custom AI ASICs — is built on ABF laminate. This single material, produced in commercial volume by essentially one company, is one of the most concentrated supply dependencies in the global technology supply chain.

BT: the workhorse substrate

Bismaleimide Triazine resin forms the core of BT substrate laminates, typically reinforced with glass fiber in BT/epoxy composites. BT substrates are more mechanically robust and thermally stable than pure ABF constructions, but support coarser linewidths — typically 15–30µm trace/space — making them unsuitable for the most advanced chip packages.

BT substrates dominate in applications where cost, volume, and mechanical reliability outweigh fine-pitch routing needs: memory packages (DRAM, NAND), automotive ICs, analog and mixed-signal chips, power devices, and most consumer electronics below the premium tier. Panasonic and Mitsubishi Gas Chemical are the primary BT resin suppliers; Kyocera, Shinko, and Nanya PCB are major fabricators.

Ceramic and Co-Fired Substrates

Before organic laminates became dominant in the 1990s, ceramics were the prestige substrate material for high-performance semiconductors. Today ceramics occupy a narrower but technically irreplaceable niche: anywhere that high thermal conductivity, extreme temperature stability, hermetic sealing, radiation hardness, or high-frequency RF performance is non-negotiable.

LTCC and HTCC: the two co-fired families

Ceramic substrates are typically fabricated via co-firing: conductor and dielectric layers are printed and pressed in "green" (unfired) form, then fired simultaneously in a kiln. HTCC (High-Temperature Co-fired Ceramic) uses alumina (Al₂O₃) or aluminum nitride (AlN) as the dielectric and tungsten or molybdenum as conductors (which survive the ~1600°C firing temperature). LTCC (Low-Temperature Co-fired Ceramic) uses glass-ceramic dielectrics and can incorporate silver or gold conductors, fired at ~850°C.

Why ceramics remain irreplaceable in defense and space

Organic substrates absorb moisture, outgas in vacuum, degrade under radiation, and have CTEs poorly matched to wide-bandgap semiconductors. For satellites, missiles, avionics, and radiation-hardened electronics, ceramic's hermetic packaging, radiation tolerance, and extreme temperature range (−55°C to +300°C operational) are not negotiable trade-offs. Kyocera and MACOM are among the leaders in high-reliability ceramic packaging for these segments.

LTCC, however, has found a rapidly growing market in 5G RF front-end modules. The ability to embed inductors, capacitors, and transmission lines inside the ceramic body — rather than placing them as surface-mount components — enables extreme miniaturization of the filtering and matching networks needed in mmWave radios. Murata, TDK, and Kyocera dominate LTCC for 5G.

Advanced Packaging Substrates: Interposers, CoWoS, and EMIB

The most consequential development in semiconductor packaging over the past decade has been the rise of advanced packaging — architectures where multiple dies, chiplets, or memory stacks are integrated at the package level rather than as monolithic silicon. This trend is driven directly by the end of Dennard scaling: if you can't make a single die faster, you can at least make the interconnect between multiple dies very short and very dense.

Advanced packaging introduces substrate structures that have no analog in conventional organic laminate packaging. The most important: the silicon interposer, the organic interposer (RDL interposer), and Intel's EMIB (Embedded Multi-die Interconnect Bridge).

Silicon interposers and their substrate context

In CoWoS (Chip-on-Wafer-on-Substrate), a large silicon interposer — patterned with fine redistribution layers (RDL) and through-silicon vias (TSVs) — sits between the dies above and the organic ABF substrate below. The interposer is itself a structured silicon wafer, processed through dedicated RDL patterning steps at TSMC. The organic ABF substrate beneath it provides the ball-grid fan-out to the PCB.

The H100, MI300X, and most other leading AI chips use this approach. The silicon interposer enables the HBM stacks to sit alongside the compute die with micro-bump interconnects at 40–55µm pitch — roughly 10× denser than anything possible on organic substrates.

EMIB: a surgical approach to the interposer problem

Intel's EMIB (Embedded Multi-die Interconnect Bridge) takes a different architectural bet. Rather than a full silicon interposer, Intel embeds small silicon bridge chips directly into the organic substrate at the locations where high-bandwidth die-to-die communication is needed. The rest of the package uses conventional organic ABF routing.

The advantage: far lower cost than a full silicon interposer, while still enabling dense (sub-10µm pitch) interconnects between adjacent die. Used in Intel's Ponte Vecchio GPU and Meteor Lake CPUs, EMIB is Intel's answer to chiplet disaggregation without the CoWoS cost premium.

Glass Substrates: The Frontier Material

Glass has long been theoretically attractive as a substrate material: ultra-smooth surfaces, tunable dielectric properties, near-zero moisture absorption, excellent dimensional stability, and the potential for very fine through-glass vias (TGVs) at lower cost than through-silicon vias. Until recently, the engineering challenges of handling thin glass at wafer and panel scale, and forming reliable copper metallization on glass surfaces, kept it in the research phase.

That changed dramatically when Intel announced in 2023 that it was targeting glass substrates for production use in the 2030s — a technology it had been developing for over a decade. Google, Samsung, and TSMC have parallel research programs. The glass substrate is now one of the most-watched materials bets in advanced packaging.

Why glass beats organic for the long term

Organic ABF substrates have a fundamental limitation: they warp under thermal cycling, particularly as package sizes grow. Larger substrates mean more warpage, which limits the die-to-substrate gap (reducing bump reliability), constrains the substrate panel size during fabrication, and requires complex warpage-compensation processes during assembly. Glass has a CTE of approximately 3.5–9 ppm/°C (tunable by composition), much closer to silicon's 2.5 ppm/°C than organic ABF's ~17 ppm/°C.

Beyond CTE, glass enables TGV formation at finer pitches and aspect ratios than organic laser-drilled vias, supports lower dielectric loss at millimeter-wave frequencies, and can in principle be manufactured in large panel formats that would dramatically reduce per-unit cost versus current silicon interposer or organic substrate processes.

The current obstacles

Glass is brittle. Handling thin glass panels (100–300µm) at the dimensions required for large-package AI chips without cracking introduces yield and throughput challenges that organic materials do not have. Copper adhesion on glass requires intermediate seed layers and surface activation steps not needed on ABF. TGV formation (typically by laser or deep reactive-ion etching) is more complex than organic laser-via drilling.

The prevailing view is that glass substrates are a genuine long-cycle technology bet rather than an imminent disruption — likely entering early production in high-value niches (AI accelerators, advanced networking) in the late 2020s and scaling through the 2030s.

Fan-Out and Embedded Die: Substrateless Packaging

A different approach to the substrate problem is to eliminate the traditional substrate entirely. Fan-out wafer-level packaging (FOWLP) and its panel-level variants (FOPLP) embed the die in a molding compound, then build redistribution layers (RDL) directly on top of the molded wafer or panel. There is no discrete substrate; the RDL replaces it.

TSMC's InFO (Integrated Fan-Out) is the highest-profile implementation — used in Apple's A-series and M-series chips (certain generations), as well as modem chips and network ASICs. The approach offers thinner packages, better thermal performance (reduced thermal resistance from die to PCB), and potentially lower cost at volume for chips where routing density requirements match InFO's capabilities (currently ~2µm L/S on advanced InFO-PoP configurations).

Embedded die in organic laminates

AT&S and Ibiden both offer embedded component packaging — where a thinned bare die is embedded inside the laminate layers of an organic substrate rather than being placed on top. This places the die at or near the neutral axis of the package, reducing warpage and enabling very short via connections from die to adjacent routing layers.

This approach is gaining traction for power management ICs, RF front-ends, and specialty processors where board-area reduction and thermal management are critical. It is technically demanding (requires precision die placement before lamination) and has so far been used in specialized rather than mainstream AI chip applications.

Critical Materials and Process Chemistry

The substrate industry's complexity is not visible on the surface. Beneath each laminate layer lies a precise stack of materials, each contributing specific electrical, mechanical, or thermal properties — and each sourced from a specialized supply chain.

The dielectric constant (Dk) and loss tangent (Df) problem

As chip-to-chip signal frequencies push into the tens of gigahertz range, the dielectric properties of the substrate material itself become a signal integrity constraint. A higher dielectric constant (Dk) slows signal propagation and increases coupling between adjacent traces. A higher loss tangent (Df) dissipates signal energy as heat. ABF resins are specifically formulated to minimize both — but the push toward 100+ Gbps serdes interfaces is driving demand for new ultra-low-Dk/Df materials that do not yet exist in high-volume production.

Supply Chain: The Chokepoints Nobody Talked About Until They Snapped

The 2020–2022 semiconductor shortage made substrate supply constraints visible to a general audience for the first time. Lead times for ABF substrates stretched to 52+ weeks. Revenue at Intel, AMD, and Qualcomm was gated not by fab capacity but by substrate availability. The underlying dynamic had been building for years: substrate capacity expansion requires multi-year construction cycles, and demand forecasting for advanced packages had systematically underestimated AI and high-performance computing growth.

The capacity expansion math problem

Building a new substrate facility takes 18–36 months from groundbreaking to first output, and 3–5 years to reach full utilization. The tools required — sequential lamination presses, laser direct-imaging (LDI) systems for fine-line patterning, electroplating lines, automated optical inspection — are themselves specialty equipment with their own supply constraints.

This creates a structural mismatch: AI chip demand can be announced and funded in 12 months; the substrate capacity to support it takes 3× longer to build. The chip companies that recognized this earliest began reserving substrate capacity years in advance — a practice that was once considered unusual but is now standard practice for any AI chip program of significance.

What AI Is Doing to Substrate Demand

AI's effect on substrate demand is not simply quantitative — more chips, more substrates. It is qualitative: AI chips require the most technically demanding substrates ever produced, at scales (both physical size and unit volume) that strain existing capacity and process capability simultaneously.

Larger die, larger substrate

An H100 SXM5 chip uses a substrate significantly larger than a conventional server CPU substrate. As advanced packaging grows to accommodate multiple chiplets and HBM stacks in a single package, substrate dimensions push toward and beyond 80mm × 80mm. Larger substrates mean larger interposers, larger ABF panels, and greater warpage management complexity — all at lower panel-level yield compared to smaller packages.

Tighter linewidths than traditional substrate processes can reach

Leading AI ASICs now require substrate trace/space at or below 2µm — comparable to an advanced PCB but not to most substrate fabricators' production capability. This concentrates advanced AI package production at a very small number of facilities (primarily Ibiden and Shinko in Japan, with selective capacity at Unimicron and AT&S), creating an effective capacity ceiling independent of investment spending.

The CoWoS capacity bottleneck of 2023–2024

The single most publicized substrate-adjacent constraint in recent years has been TSMC's CoWoS packaging capacity. H100 GPU shipments in 2023 were directly constrained by CoWoS-S throughput at TSMC — not by N4 wafer starts. This was a vivid demonstration that the substrate and advanced packaging layer had become the binding constraint in AI chip supply, above the wafer fab itself. TSMC responded with aggressive CoWoS capacity expansion that nearly doubled throughput by end of 2024.

Custom ASICs and the substrate supply ripple effect

Google TPUs, Amazon Trainium/Inferentia, Meta MTIA, Microsoft Maia, and a wave of AI chip startups all require advanced ABF substrates and, in many cases, advanced interposer packaging. This diversifies the demand pool beyond just NVIDIA and AMD, applying sustained pressure on advanced substrate capacity across a broader customer base than at any previous point in semiconductor history.

Where the Substrate Roadmap Leads

The substrate industry is undergoing its most significant technology transition since the shift from wire-bond to flip-chip packaging in the 2000s. Several vectors of change are operating simultaneously, and their convergence will determine the physical limits of the next generation of AI hardware.

The physics limits that substrates must outpace

The transistor density on leading AI chips is growing faster than substrate interconnect density. This gap — between what the silicon inside can do and what the substrate beneath it can connect — is the fundamental tension driving the glass substrate effort, the move to silicon interposers, and ultimately the interest in wafer-scale integration as an architecture where the chip and its substrate become a single fabricated object. Cerebras's Wafer-Scale Engine is the current most visible extreme of this direction.

Conclusion: The Material That Runs Beneath Everything

The substrate story is, at its core, a story about what happens when the supporting cast becomes as strategically important as the headline act. For three decades, semiconductor packaging substrates were enablers — unremarkable laminates that made chips pluggable into boards. The complexity was assumed to reside in the silicon.

The AI era has exposed how dependent chip performance, chip supply, and chip cost actually are on what sits between the die and the board. A single Japanese food company's specialty film underpins every advanced CPU and GPU. A handful of Japanese laminate fabricators gate global AI chip production. A packaging step at TSMC — not the fab — was the binding constraint on H100 supply during the most intense AI hardware demand cycle in history.

The substrate will get more important before it becomes easier. Larger packages, finer lines, tighter tolerances, new materials, new geometries, and new physics regimes await. The companies that understand this layer deeply — and invest accordingly — will have leverage over the AI hardware supply chain that no amount of compute-benchmark leadership can substitute.